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[Other resourceref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031656 | Author: 包盛花 | Hits:

[Other resourceref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 微波炉定时控制器的设计,已成功经过调试,并有相应的课程设计报告-Microwave oven controller design from time to time, after successfully testing and a corresponding report of the curriculum design
Platform: | Size: 187392 | Author: 林君霞 | Hits:

[SCMcontroller

Description: PID controller .....source code-PID controller .....source code..................
Platform: | Size: 1024 | Author: kiran | Hits:

[VHDL-FPGA-Verilogads7844

Description: ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller
Platform: | Size: 1386496 | Author: tom | Hits:

[Program docVHDL

Description: 本文是基于VHDL语言的洗衣机控制器设计与仿真的源代码,并且内附详细解析,对初学者有很大的帮助-This article is based on the VHDL language, washing machine controller design and simulation of the source code, and included detailed analysis, there is a great help for beginners
Platform: | Size: 258048 | Author: | Hits:

[VHDL-FPGA-Verilogcontroller

Description: PI controller and its source code
Platform: | Size: 2048 | Author: sanjivkumar | Hits:

[File Formatdlx-controller

Description: vhdl controller, but dunno right or wrong-vhdl controller, but dunno right or wrong..
Platform: | Size: 1024 | Author: ivan | Hits:

[Embeded-SCM DevelopADS7844VHDL

Description: ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller
Platform: | Size: 1174528 | Author: 李传敏 | Hits:

[Otherwashing

Description: VHDL实现洗衣机控制器程序,功能描述:1. 洗衣机的工作步骤为洗衣、漂洗和脱水三个过程,工作时间分别为:洗衣20 秒,漂洗30 秒,脱水15 秒;可以单独选择其中某一项功能;2. 用显示器件显示洗衣机的工作状态,并倒计时显示每个状态的工作时间, 全部过程结束后,应提示使用者;3. 洗衣过程可以暂停,重新启动后恢复原状态;4、 可以预约洗衣时间。-VHDL controller to achieve washing procedure, function description: 1. The work steps for laundry washing, rinsing and dehydration three processes, working hours are: laundry 20 seconds, rinse for 30 seconds, dehydrated for 15 seconds can individually choose a particular function 2. using display devices display the working status of washing machine, and the countdown show the working hours of each state, all the process is finished, should prompt the user 3. laundry process can pause, restart after the restoration of the original state 4, can appointment laundry.
Platform: | Size: 61440 | Author: 雨姿 | Hits:

[VHDL-FPGA-VerilogSDRAM-controller-design-FPGA-based

Description: 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
Platform: | Size: 3163136 | Author: connie | Hits:

[VHDL-FPGA-VerilogSD-card-controller-used--FPGA

Description: SD卡控制器的FPGA实现 -SD card controller FPGA to achieve SD card controller FPGA implementation
Platform: | Size: 257024 | Author: liujie | Hits:

[VHDL-FPGA-VerilogPS2-keyboard-controller-design

Description: PS2 keyboard controller design PS2 键盘控制设计-PS2 keyboard controller design
Platform: | Size: 871424 | Author: liu | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk,产生的时钟信号clk送往寄存器与状态控制器,时钟信号clk2送往数据控制器与状态控制器,信号fetch送往数据控制器与地址多路器,信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk.
Platform: | Size: 4096 | Author: cccs | Hits:

[VHDL-FPGA-Verilogparallel-output-controller-(POC)

Description: 并行输出控制器,实现CPU与打印机之间的通信,程序基于VHDL语言,内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provided for simulation.
Platform: | Size: 74752 | Author: 陈鹏 | Hits:

[VHDL-FPGA-VerilogSix-story-elevator-controller

Description: 六层电梯控制器,这个很不错的,分享给大家-Six-story elevator controller, this is very good to share for everyone
Platform: | Size: 3072 | Author: 木三清 | Hits:

[VHDL-FPGA-VerilogStepper-motor-controller-

Description: 步进电机控制器,单机反馈自动控制,vhdl代码。-Stepper motor controller
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-VerilogNandFlash-FPGA-controller(ECC)

Description: 该压缩包包括NAND FLASH(美光)的FPGA控制器的原理及VHDL源码,非常具有参考价值。-The archive includes NAND FLASH (Micron) the principle of the FPGA and VHDL source code control, very valuable reference.
Platform: | Size: 1587200 | Author: 张明利 | Hits:

[VHDL-FPGA-Verilogpid-controller

Description: vhdl source code for pid controller on fpga
Platform: | Size: 4096 | Author: reza | Hits:

[VHDL-FPGA-VerilogDC-motor-controller-and-its-control

Description: 基于VHDL语言的直流电机控制器及其控制,本控制系统的总体结构,下位机是整个高频疲劳试验机控制器的核心。用于实现产生控制试验机的控制信号和数据,反馈信号的处理,以及和上位机进行数据通信。其控制功能强弱也直接影响着整个控制器性能的好坏-DC Motor Based on VHDL controller and its control, the overall structure of the control system, the next bit machine is the high-frequency fatigue test machine controller core. Control the testing machine used to implement the resulting control signal and data processing of the feedback signal, and the host computer and data communication. The strength of its control functions have a direct impact on the performance of the controller is good or bad
Platform: | Size: 3072 | Author: moyeo | Hits:
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